A pipelined architecture is an architecture for design of a computer system of performing parallel processes. In this design architecture, one processor is divided into several sub-processors having different functions, which are simultaneously performed to process different data. In general, in a computer, instructions are processed through five stages of fetching, analyzing, content-fetching, executing, and storing stages, and thus, the instructions are processed by the computer processor in the input order thereof step by step. However, in the pipelined architecture, since the instructions can be processed in parallel, the processing rate can be increased.
In the pipelined architecture, a time taken for completing five stages with respect to one instruction is defined by an instruction cycle; and a time taken at each stage is defined by a pipeline cycle. If the pipeline cycle is maintained constant, the five stages can be operated synchronously, so that it is possible to easily control the computer system. In order to design the pipelined architecture so that the pipeline cycles are equal, the stage having the longest time is set as a reference stage. In the case where the pipeline cycles are not constant, buffers are installed between the stages so that the stages continue to be operated asynchronously.
In some cases, the pipelined architecture may be divided into instruction pipelines and arithmetic pipelines. The instruction pipeline denotes a stage where instructions are moved through the processor. In the stage of the instruction pipeline, fetching, buffer storing, and execution are included. The arithmetic pipeline denotes a portion of calculation arithmetic which can be divided and overlappedly executed. On the other hand, according to a memory stage system, the pipeline architecture may be adapted to a memory controller which moves data to several locations.